fhdl/verilog: fix dummy signal initial event
authorSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 18 Mar 2015 23:24:30 +0000 (00:24 +0100)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Wed, 18 Mar 2015 23:24:30 +0000 (00:24 +0100)
commit7fa1cd72a8d354409087dc8b001a5eeb7a4385d2
tree87e5eda5df5da87886ab28cca6004c65546eecfb
parent3aee58f484a7b659b0d002f0e554a8d8bb87afbe
fhdl/verilog: fix dummy signal initial event
migen/fhdl/verilog.py