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(parent: 24ac3f6) | patch
back.rtlil: fix sim-synth mismatch with assigns following switches.
authorwhitequark <cz@m-labs.hk>
Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)
committerwhitequark <cz@m-labs.hk>
Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)
commit7fdd0c055ab9d410d12af1121a7759e54485e295
tree47170037165563df9444ec1541fd773972610cbbtree
parent24ac3f68a1f057d9b3a29baf05d8e2a528b81738commit | diff
back.rtlil: fix sim-synth mismatch with assigns following switches.

Closes #155.
nmigen/back/rtlil.py diff | blob | history