write_verilog: correctly map RTLIL `sync init`.
authorwhitequark <whitequark@whitequark.org>
Fri, 7 Dec 2018 18:48:06 +0000 (18:48 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 7 Dec 2018 18:55:08 +0000 (18:55 +0000)
commit7fe770a441a129c509fd4da04b60ada942a28bc8
tree03cb149cb5da3a9638b5919019db38ee6b754db7
parent435776120a40ed06ea42ca63bcca231913507ac3
write_verilog: correctly map RTLIL `sync init`.
backends/verilog/verilog_backend.cc