add misaligned mem test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:26:45 +0000 (13:26 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:26:45 +0000 (13:26 +0000)
commit80409ead286395a7f359a8ceb3ccb22ac9ee1562
treede003ed8134983b4269daf4c348260cb7d797699
parent70498a68baab54982ffaf2300f51d77d21c1b252
add misaligned mem test
src/openpower/decoder/isa/mem.py
src/openpower/decoder/isa/test_mem.py