[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
authorMatthew Wahab <matthew.wahab@arm.com>
Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)
committerMatthew Wahab <matthew.wahab@arm.com>
Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)
commit80776b29d60ebdcd3631604858f144a72b8bcb8e
tree28a11f5b1637d53389c37442cc5041175c59093e
parentf3aa142b8b04bfccef2cbc3233b565c2b3faa01a
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.

The general form for these instructions is
  <OP> <Hd>, <Hs>
or
  <OP> <Hd>, <Hs>, #0.0

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.

Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
gas/testsuite/ChangeLog
gas/testsuite/gas/aarch64/advsimd-fp16.d
gas/testsuite/gas/aarch64/advsimd-fp16.s
opcodes/ChangeLog
opcodes/aarch64-asm-2.c
opcodes/aarch64-dis-2.c
opcodes/aarch64-opc-2.c
opcodes/aarch64-tbl.h