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(parent: 2d1e521) | patch
initialise overflow to zero in setvl, unconditionally.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Aug 2022 18:39:05 +0000 (19:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Aug 2022 18:39:05 +0000 (19:39 +0100)
commit80ad71609c45ad9bb4f93c6836487dc0d00f584f
treeb6bdc8f72f94e1644de2cd1b591e5144e5bc01e8tree
parent2d1e5215b1089fa7e2f1bfba53f6d012ba6dd927commit | diff
initialise overflow to zero in setvl, unconditionally.
add two new CTR-mode/Rc=1 setvl. tests, to confirm that overflow
does/does-not occur correctly when CTR is used as input to set VL
openpower/isa/simplev.mdwn diff | blob | history
src/openpower/decoder/isa/test_caller_setvl.py diff | blob | history