projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2b9c75f) | patch
reg_wire_error test needs the -sv flag so it is run via a script so it had to be...
authorUdi Finkelstein <github@udifink.com>
Tue, 5 Jun 2018 09:15:59 +0000 (12:15 +0300)
committerUnknown <github@udifink.com>
Tue, 5 Jun 2018 15:00:06 +0000 (18:00 +0300)
commit80d9d15f1c4b73ee73172b06fd2c8c55703aea54
tree68d7f6d234399e075af592d16d4f9120c714be25tree
parent2b9c75f8e372f6886e073743d1df11bcd1c58281commit | diff
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
tests/simple/reg_wire_error.v [deleted file] blob | history
tests/various/reg_wire_error.sv [new file with mode: 0644] blob
tests/various/reg_wire_error.ys [new file with mode: 0644] blob