Merge pull request #1393 from whitequark/write_verilog-avoid-init
authorClifford Wolf <clifford@clifford.at>
Sun, 27 Oct 2019 09:25:01 +0000 (10:25 +0100)
committerGitHub <noreply@github.com>
Sun, 27 Oct 2019 09:25:01 +0000 (10:25 +0100)
commit81876a3734dacde199446343ce338b24e9b2796f
treef637930db9d29efaeb4609017f07761f012b6d99
parent84982b308343315c889d3d00116db820a51cad78
parent4f426c2ac48bbb5ae9e92ca046aa20af35d75a52
Merge pull request #1393 from whitequark/write_verilog-avoid-init

write_verilog: do not print (*init*) attributes on regs