projects / yosys.git / commit
| author | Diego H <dhdezr@gmail.com> | |
| Tue, 4 Dec 2018 02:08:35 +0000 (20:08 -0600) | ||
| committer | Diego H <dhdezr@gmail.com> | |
| Tue, 4 Dec 2018 02:08:35 +0000 (20:08 -0600) | ||
| commit | 819ca7309620b3791c7b93de44990ffb4fceb30f | |
| tree | 08fd9f5adfd9a8afb3f58600e67907c7346b0cee | tree |
| parent | 47c89d600c11aee97e325351d295781169d62978 | commit | diff |
| techlibs/gowin/Makefile.inc | diff | blob | history | |
| techlibs/gowin/arith_map.v | [new file with mode: 0644] | blob |
| techlibs/gowin/cells_sim.v | diff | blob | history | |
| techlibs/gowin/synth_gowin.cc | diff | blob | history | |
| techlibs/intel/common/brams_map.v | diff | blob | history |