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(parent: 2a8d5e6) | patch
Use left-recursive rule for cell_port_list in Verilog parser.
authorAndrew Becker <andrew.becker@epfl.ch>
Mon, 14 Mar 2016 18:28:34 +0000 (19:28 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 15 Mar 2016 11:03:40 +0000 (12:03 +0100)
commit81d4e9e7c1c311f837dadb1634c83b4e70929669
tree868cecfa8e060a8308977470ebd9e2812e7d6ce4tree
parent2a8d5e64f5a994fa8f4f51c00d647ad977e42e4bcommit | diff
Use left-recursive rule for cell_port_list in Verilog parser.
frontends/verilog/verilog_parser.y diff | blob | history