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(parent: d680eba) | patch
add first peripheral set
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 22 Jul 2018 06:49:39 +0000 (07:49 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 22 Jul 2018 06:49:39 +0000 (07:49 +0100)
commit821a48963171cf5a7cb3848a8d5203f933d16757
tree1bdc2c620ffdcfd333bb0af7efae26bc1c134b38tree
parentd680eba828025244788d6df848d771daced753b0commit | diff
add first peripheral set
19 files changed:
src/lib/ClockDiv.bsv [new file with mode: 0644] blob
src/lib/ConcatReg.bsv [new file with mode: 0644] blob
src/lib/axi_addr_generator.bsv [new file with mode: 0644] blob
src/peripherals/gpio/gpio.bsv [new file with mode: 0644] blob
src/peripherals/i2c/I2C_Defs.bsv [new file with mode: 0644] blob
src/peripherals/i2c/I2C_top.bsv [new file with mode: 0644] blob
src/peripherals/plic/plic.bsv [new file with mode: 0644] blob
src/peripherals/pwm/pwm.bsv [new file with mode: 0644] blob
src/peripherals/qspi/qspi.bsv [new file with mode: 0644] blob
src/peripherals/qspi/qspi.defs [new file with mode: 0644] blob
src/peripherals/sdmmc/sdcard_dummy.bsv [new file with mode: 0644] blob
src/peripherals/uart/RS232_modified.bsv [new file with mode: 0644] blob
src/peripherals/uart/Uart16550.bsv [new file with mode: 0644] blob
src/peripherals/uart/Uart_bs.bsv [new file with mode: 0644] blob
src/uncore/axi4/AXI4_Fabric.bsv [new file with mode: 0644] blob
src/uncore/axi4/AXI4_Types.bsv [new file with mode: 0644] blob
src/uncore/axi4/Cur_Cycle.bsv [new file with mode: 0644] blob
src/uncore/axi4/Semi_FIFOF.bsv [new file with mode: 0644] blob
src/uncore/axi4lite/AXI4Lite_AXI4_Bridge.bsv [new file with mode: 0644] blob
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