i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 21 Apr 2014 23:37:04 +0000 (16:37 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 3 Nov 2014 23:32:43 +0000 (15:32 -0800)
commit822e791321c387cadcec562820a0521aae90cc77
tree284173651bc01e679ab70c1cff205f807890ceb6
parente813728b2b7cba0c5aa4cad7a3eee909dc7afcc0
i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.

Skylake has some extra bits in PIPELINE_SELECT, none of which are
interesting for a 3D driver.  In order to selectively change them, it
also introduces new "mask bits" in 15:8.  We care about the "Pipeline
Selection" bits (1:0), so set the mask to 0x3.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
src/mesa/drivers/dri/i965/brw_misc_state.c