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i965/vec4: Clamp indirect tes input array reads with 0x0fffffff
authorIan Romanick <ian.d.romanick@intel.com>
Tue, 19 Jun 2018 00:02:58 +0000 (17:02 -0700)
committerIan Romanick <ian.d.romanick@intel.com>
Sat, 1 Sep 2018 07:23:45 +0000 (00:23 -0700)
commit82530ce1b5a76ce1835ed573411ed26cc2338a3e
tree63bcd80745751976566039c2303cd1306667251btree
parent75666605c98e628ad6a88ef46ec7351588969ed5commit | diff
i965/vec4: Clamp indirect tes input array reads with 0x0fffffff

Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid
range of the offset is [0, 0FFFFFFFh].

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
src/intel/compiler/brw_vec4_tes.cpp diff | blob | history