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(parent: 7566f04) | patch
liteeth: Hook up LiteX LiteEth ethernet controller
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Sat, 13 Jun 2020 00:04:31 +0000 (10:04 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 23 Jun 2020 23:53:01 +0000 (09:53 +1000)
commit8366710217d4f1a7b84164eaa715edc4378c8988
tree004832c4e64ba493f9a00234294402c9c4149ed5tree
parent7566f04fe3f0807cde42b1965feae57fe4346476commit | diff
liteeth: Hook up LiteX LiteEth ethernet controller

Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
15 files changed:
fpga/arty_a7.xdc diff | blob | history
fpga/top-arty.vhdl diff | blob | history
include/microwatt_soc.h diff | blob | history
litedram/gen-src/sdram_init/main.c diff | blob | history
litedram/generated/arty/litedram_core.init diff | blob | history
litedram/generated/nexys-video/litedram_core.init diff | blob | history
litedram/generated/sim/litedram_core.init diff | blob | history
liteeth/fusesoc-add-files.py [new file with mode: 0644] blob
liteeth/gen-src/arty.yml [new file with mode: 0644] blob
liteeth/gen-src/generate.sh [new file with mode: 0755] blob
liteeth/generated/arty/liteeth_core.v [new file with mode: 0644] blob
liteeth/liteeth.core [new file with mode: 0644] blob
microwatt.core diff | blob | history
soc.vhdl diff | blob | history
syscon.vhdl diff | blob | history