cores/clock: add initial Spartan6 PLL/DCM support
authorMichael Betz <michibetz@gmail.com>
Tue, 23 Apr 2019 04:23:00 +0000 (06:23 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 23 Apr 2019 04:23:00 +0000 (06:23 +0200)
commit83699ea0a5105e54cbcdd626801294048eddb3ff
tree0c98f5e9bbe260688f5de3b03ac5a7acbcae95f6
parenteff141da2d9910fe2ad45724d6d96ba632eddce7
cores/clock: add initial Spartan6 PLL/DCM support
litex/soc/cores/clock.py
litex/soc/cores/cpu/vexriscv/verilog