Merge pull request #1109 from YosysHQ/clifford/fix1106
authorClifford Wolf <clifford@clifford.at>
Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)
committerGitHub <noreply@github.com>
Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)
commit8395f837c33a1f08ed67995ef8274219b0af27c8
treee4fa22a4a4598e86f0fa324741fb6062dca851e8
parent5a1f1caa44fb3f4427813acab61aaecc06bae7ba
parentec4565009ae69409eb01f1b595f5f59fcc969ce2
Merge pull request #1109 from YosysHQ/clifford/fix1106

Add "read_verilog -pwires" feature