[AArch64] Add missing C_MAX_ELEM flags for SVE conversions

[AArch64] Add missing C_MAX_ELEM flags for SVE conversions

SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.

Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.

gas/
	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
	SCVTF, UCVTF, LSR and ASR.
	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.