Merge pull request #10 from hansiglaser/master
authorClifford Wolf <clifford@clifford.at>
Wed, 21 Aug 2013 16:47:06 +0000 (09:47 -0700)
committerClifford Wolf <clifford@clifford.at>
Wed, 21 Aug 2013 16:47:06 +0000 (09:47 -0700)
commit8409956c0c1b96b69f7b43085a9fe943f23a597f
tree83aaefcdecb3a036bf1eaff3b3cb4e5ffbfb3f32
parentf8107ab7fc90dc3458769c9fe6bab0eb5c159368
parentf352205635ddc5f5e872eafb4eebb4f770440d2b
Merge pull request #10 from hansiglaser/master

fixed Verilog parser filename and line numbering issue with include files