mem-ruby: MESI_Three_Level fix L1 in_port ranks
authorTimothy Hayes <timothy.hayes@arm.com>
Fri, 18 Oct 2019 15:43:00 +0000 (16:43 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 20 Mar 2020 13:25:11 +0000 (13:25 +0000)
commit8430889fa765477e0d477dc849aec829638e147e
tree77d41b7e13d6b79969aa3eaef48a6ac83f4e2541
parentcd69bb50414450c3bb5ef41dce676b75fd42c0ee
mem-ruby: MESI_Three_Level fix L1 in_port ranks

The L1 cache contains three in_port networks with ranks 0-2-3.
This is a benign typo, however, this patch corrects the ranks to
0-1-2 for clarity.

Change-Id: Id9bb63dae310af0f962345a114b0ccb8bddcf696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24257
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm