Merge pull request #1359 from YosysHQ/xc7dsp
authorEddie Hung <eddie@fpgeh.com>
Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)
committerGitHub <noreply@github.com>
Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)
commit8474c5b366660153cae03a9de4af8e1ed809856d
treecd157ab16b528565ced19f422ffece1c6110f53e
parentce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3
parentb3d8a60cbd94176076f23c4ea6c94ec24e6773e0
Merge pull request #1359 from YosysHQ/xc7dsp

DSP inference for Xilinx (improved for ice40, initial support for ecp5)
backends/aiger/xaiger.cc
techlibs/xilinx/abc_xc7.box
techlibs/xilinx/synth_xilinx.cc