Improve naming scheme for (VHDL) modules imported from Verific
authorClifford Wolf <clifford@clifford.at>
Thu, 24 Oct 2019 10:13:37 +0000 (12:13 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 24 Oct 2019 10:13:50 +0000 (12:13 +0200)
commit84982b308343315c889d3d00116db820a51cad78
tree9eabe561c9a24e57bddff83886e996c015bd3e3c
parent34dadd9ab20494057c1ac7dae443b48eee0c2c30
Improve naming scheme for (VHDL) modules imported from Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/verific/verific.cc