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(parent: e799019) | patch
back.{rtlil,verilog}: split convert_fragment() off convert().
authorwhitequark <cz@m-labs.hk>
Mon, 19 Aug 2019 19:27:02 +0000 (19:27 +0000)
committerwhitequark <cz@m-labs.hk>
Mon, 19 Aug 2019 19:49:51 +0000 (19:49 +0000)
commit84d19abbdee57c6a0efed0a282ee2fe8ec2b956d
treeaecfa394beeed9931712b3ce1c6594416d4c2103tree
parente7990197db52f4331a6f58bd57aaeb1d8788330ccommit | diff
back.{rtlil,verilog}: split convert_fragment() off convert().

Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
nmigen/back/rtlil.py diff | blob | history
nmigen/back/verilog.py diff | blob | history
nmigen/compat/fhdl/verilog.py diff | blob | history