git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Thu, 25 Oct 2018 08:28:33 +0000 (09:28 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Thu, 25 Oct 2018 08:28:33 +0000 (09:28 +0100)
commit	84e8c5b9c1a88990e368709f9ca08b910336cac1
tree	82f537845b387a387870cef2d97fb6604a601eb9	tree
parent	e2b71c848f2e12c27bb2ac304d5e22d4929d3b0c	commit \| diff

redirect DO_WRITE_FREG and READ_FREG and others

no longer adding the offset onto the register in sv_insn_t,
now to be done in sv_proc_t WRITE_REG/READ_REG, where the
element width can be examined (finally)

riscv/insn_template_sv.cc		diff \| blob \| history
riscv/sv.cc		diff \| blob \| history
riscv/sv_insn_redirect.cc		diff \| blob \| history
riscv/sv_insn_redirect.h		diff \| blob \| history

Simple-V augmented version of spike

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