[ARM][GCC][13x]: MVE ACLE scalar shift intrinsics.
This patch supports following MVE ACLE scalar shift intrinsics.
sqrshr, sqrshrl, sqrshrl_sat48, sqshl, sqshll, srshr, srshrl, uqrshl, uqrshll, uqrshll_sat48, uqshl, uqshll, urshr, urshrl, lsll, asrl.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
(UQSHL_QUALIFIERS): Likewise.
(ASRL_QUALIFIERS): Likewise.
(SQSHL_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
Big-Endian Mode.
(sqrshr): Define macro.
(sqrshrl): Likewise.
(sqrshrl_sat48): Likewise.
(sqshl): Likewise.
(sqshll): Likewise.
(srshr): Likewise.
(srshrl): Likewise.
(uqrshl): Likewise.
(uqrshll): Likewise.
(uqrshll_sat48): Likewise.
(uqshl): Likewise.
(uqshll): Likewise.
(urshr): Likewise.
(urshrl): Likewise.
(lsll): Likewise.
(asrl): Likewise.
(__arm_lsll): Define intrinsic.
(__arm_asrl): Likewise.
(__arm_uqrshll): Likewise.
(__arm_uqrshll_sat48): Likewise.
(__arm_sqrshrl): Likewise.
(__arm_sqrshrl_sat48): Likewise.
(__arm_uqshll): Likewise.
(__arm_urshrl): Likewise.
(__arm_srshrl): Likewise.
(__arm_sqshll): Likewise.
(__arm_uqrshl): Likewise.
(__arm_sqrshr): Likewise.
(__arm_uqshl): Likewise.
(__arm_urshr): Likewise.
(__arm_sqshl): Likewise.
(__arm_srshr): Likewise.
* config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
qualifier.
(UQSHL_QUALIFIERS): Likewise.
(ASRL_QUALIFIERS): Likewise.
(SQSHL_QUALIFIERS): Likewise.
* config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
(mve_sqrshrl_sat<supf>_di): Likewise.
(mve_uqrshl_si): Likewise.
(mve_sqrshr_si): Likewise.
(mve_uqshll_di): Likewise.
(mve_urshrl_di): Likewise.
(mve_uqshl_si): Likewise.
(mve_urshr_si): Likewise.
(mve_sqshl_si): Likewise.
(mve_srshr_si): Likewise.
(mve_srshrl_di): Likewise.
(mve_sqshll_di): Likewise.
gcc/testsuite/ChangeLog:
2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/asrl.c: New test.
* gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshll_sat64.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
* lib/target-supports.exp:
(check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Modify to not
support MVE floating point in Big Endian mode.
(check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to not
support MVE integer in Big Endian mode.
23 files changed:
projects / gcc.git / commit