projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 038e1bc) | patch
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_l...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 25 Apr 2020 10:11:10 +0000 (12:11 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 25 Apr 2020 10:11:10 +0000 (12:11 +0200)
commit85a059bf773f9224bdd7106dbc5c8639d20d3af2
treedba3d5ca398a964046d5c265b30d10ee079aec1ctree
parent038e1bc048731e55856999622c3a2c7ff45bb050commit | diff
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.

We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
litex/soc/software/bios/sdram.c diff | blob | history