projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: eab3272) | patch
synth_intel: a10gx -> arria10gx
authorDan Ravensloft <dan.ravensloft@gmail.com>
Tue, 10 Dec 2019 13:40:32 +0000 (13:40 +0000)
committerDan Ravensloft <dan.ravensloft@gmail.com>
Tue, 10 Dec 2019 13:48:10 +0000 (13:48 +0000)
commit85a14895ca31ec8c34bf5c296a5740a798b06693
treeca6e9e7d1166086c7085be3febba006ccdb1df78tree
parenteab3272cdeed697bdb9664c2d8a133d336addb7ccommit | diff
synth_intel: a10gx -> arria10gx
techlibs/intel/Makefile.inc diff | blob | history
techlibs/intel/a10gx/cells_arith.v [deleted file] blob | history
techlibs/intel/a10gx/cells_map.v [deleted file] blob | history
techlibs/intel/a10gx/cells_sim.v [deleted file] blob | history
techlibs/intel/arria10gx/cells_arith.v [new file with mode: 0644] blob
techlibs/intel/arria10gx/cells_map.v [new file with mode: 0644] blob
techlibs/intel/arria10gx/cells_sim.v [new file with mode: 0644] blob
techlibs/intel/synth_intel.cc diff | blob | history