back.verilog: detect undriven public wires using Yosys.
authorwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 04:51:15 +0000 (04:51 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 04:59:48 +0000 (04:59 +0000)
commit85b16025d35561e81cca633b6fbf6cbf0b10f333
treeff2c9ee2243e66893e31fe2c57e5ad720c412012
parent33fb3497e916f5d905c898bcc78f68881b1c5e8d
back.verilog: detect undriven public wires using Yosys.

This should never happen, and is certainly a logic bug in nMigen.
nmigen/back/verilog.py