mem-ruby: L3 hit/miss tracking to MOESI_AMD_BASE-dir
authorDaniel Gerzhoy <daniel.gerzhoy@gmail.com>
Wed, 23 Sep 2020 20:39:08 +0000 (16:39 -0400)
committerDaniel Gerzhoy <daniel.gerzhoy@gmail.com>
Thu, 22 Oct 2020 14:45:34 +0000 (14:45 +0000)
commit85ede9a1808273beddaa2cb0b59fbb378199bfd4
tree98813b0a69367f50c0160404f095089bd18a37d2
parent076a0e1f5f432842d5a3b2df2ad1aaf1f94ca927
mem-ruby: L3 hit/miss tracking to MOESI_AMD_BASE-dir

L3 access tracking added to the directory controller.

This commit adds L3 hit/miss tracking to the controller.
Hit/miss status is decided when the tag array of the
L3 Cache is checked for the first time for any given request.

Change-Id: Icac122f59509d79135265fb38b112d3f47419b6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33314
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm