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(parent: 0d248dd) | patch
Revert "Special abc9_clock wire to contain only clock signal"
authorEddie Hung <eddie@fpgeh.com>
Thu, 5 Dec 2019 19:11:53 +0000 (11:11 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 5 Dec 2019 19:11:53 +0000 (11:11 -0800)
commit864bff14f11fc67bac40f77e5bf17c7fc61ad9f6
tree17469a61dc43464cd8281cc046a8c9df3702d0a1tree
parent0d248dd7bae707505071b309b55bac75facccab8commit | diff
Revert "Special abc9_clock wire to contain only clock signal"

This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
techlibs/xilinx/abc9_map.v diff | blob | history