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(parent: 62fbfbe) | patch
create first litex-hub pythondata_cpu_libresoc repo
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 11:35:56 +0000 (12:35 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 11:35:56 +0000 (12:35 +0100)
commit86832db35effb519e7c5da46f59010aea2acb073
tree006010a7bedb391a651840aafe6824c54d712d34tree
parent62fbfbe76f884bd3238c696de7f367bf2d6b06f4commit | diff
create first litex-hub pythondata_cpu_libresoc repo
based on microwatt but using vexrisc principle due to source code size being
absolutely massive (130,000 lines across multiple repositories)
MANIFEST.in [new file with mode: 0644] blob
Makefile [new file with mode: 0644] blob
README.md [new file with mode: 0644] blob
pythondata_cpu_libresoc/__init__.py [new file with mode: 0644] blob
pythondata_cpu_libresoc/verilog/libresoc.v [new file with mode: 0644] blob
requirements.txt [new file with mode: 0644] blob
setup.py [new file with mode: 0644] blob
test.py [new file with mode: 0644] blob