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(parent: ab97edd) | patch
Make return value of $clog2 signed
authorSylvain Munaut <tnt@246tNt.com>
Sat, 24 Nov 2018 17:49:23 +0000 (18:49 +0100)
committerSylvain Munaut <tnt@246tNt.com>
Sat, 24 Nov 2018 17:49:23 +0000 (18:49 +0100)
commit86ce43999eaed10c3b9d141bb2f66bf98ad45eb6
treeea2c9ab46c74f01f79828ea4fae9f32feefef677tree
parentab97eddee9b0ea0a772660731fe4c3270d2564e5commit | diff
Make return value of $clog2 signed

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
frontends/ast/simplify.cc diff | blob | history