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(parent: 40e3599) | patch
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
authorMarcelina Kościelnicka <mwk@0x04.net>
Wed, 16 Dec 2020 23:24:48 +0000 (00:24 +0100)
committerMarcelina Kościelnicka <mwk@0x04.net>
Thu, 17 Dec 2020 02:25:07 +0000 (03:25 +0100)
commit871fc34ad43dac0ff924b8f72a0524d937040190
treecc1837956ea7816b5990ec2bfbb2c3290ff49dbatree
parent40e35993af6ecb6207f15cc176455ff8d66bcc69commit | diff
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.

These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
techlibs/xilinx/cells_xtra.py diff | blob | history
techlibs/xilinx/cells_xtra.v diff | blob | history