Improve TI mode address offsets - these may either use LDP of 64-bit or LDR of 128...

Improve TI mode address offsets - these may either use LDP of 64-bit or LDR of 128-bit...

Improve TI mode address offsets - these may either use LDP of 64-bit or
LDR of 128-bit, so we need to use the correct intersection of offsets.
When splitting a large offset into base and offset, use a signed 9-bit
unscaled offset.

Remove the Ump constraint on movti and movtf instructions as this blocks
the reload optimizer from merging address CSEs (is this supposed to work
only on 'm' constraints?).  The result is improved codesize, especially
wrf and gamess in SPEC2006.

    gcc/
	* config/aarch64/aarch64.md (movti_aarch64): Change Ump to m.
	(movtf_aarch64): Likewise.
	* config/aarch64/aarch64.c (aarch64_classify_address):
	Use correct intersection of offsets.
	(aarch64_legitimize_address_displacement): Use 9-bit signed offsets.
	(aarch64_legitimize_address): Use 9-bit signed offsets for TI/TF mode.
	Use 7-bit signed scaled mode for modes > 16 bytes.

From-SVN: r243346