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(parent: 3ede67a) | patch
r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled
authorMichel Dänzer <michel.daenzer@amd.com>
Wed, 8 Oct 2014 07:01:47 +0000 (16:01 +0900)
committerMichel Dänzer <michel@daenzer.net>
Wed, 15 Oct 2014 07:26:14 +0000 (16:26 +0900)
commit87da286755ea09b6efab591a124c261fde890ba8
tree9fee5a861f91b5f8044ff73771f59d1ddef6e7c4tree
parent3ede67a4c6d77892296ffc5568ddf3accaa1af99commit | diff
r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled

We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
access may not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeon/r600_texture.c diff | blob | history