git.libre-soc.org Git - binutils-gdb.git/commit

author	Mike Frysinger <vapier@gentoo.org>
	Sun, 25 Dec 2022 05:53:25 +0000 (00:53 -0500)
committer	Mike Frysinger <vapier@gentoo.org>
	Sun, 25 Dec 2022 07:10:46 +0000 (02:10 -0500)
commit	883be197745c9a9ea626cf0671e8bb0109d21a36
tree	0c19d5fa5fb39952a439f495c29c32e5ea777738	tree
parent	fc9b04458287e58365b1de8eaf6b626ac11743c2	commit \| diff

sim: cpu: change default init to handle all cpus

All the runtimes were only initializing a single CPU. When SMP is
enabled, things quickly crash as none of the other CPU structs are
setup. Change the default from 0 to the compile time value.

28 files changed:

sim/aarch64/interp.c		diff \| blob \| history
sim/arm/wrapper.c		diff \| blob \| history
sim/avr/interp.c		diff \| blob \| history
sim/bfin/interp.c		diff \| blob \| history
sim/bpf/sim-if.c		diff \| blob \| history
sim/common/sim-cpu.c		diff \| blob \| history
sim/cr16/interp.c		diff \| blob \| history
sim/cris/sim-if.c		diff \| blob \| history
sim/d10v/interp.c		diff \| blob \| history
sim/example-synacor/interp.c		diff \| blob \| history
sim/frv/sim-if.c		diff \| blob \| history
sim/ft32/interp.c		diff \| blob \| history
sim/h8300/compile.c		diff \| blob \| history
sim/iq2000/sim-if.c		diff \| blob \| history
sim/lm32/sim-if.c		diff \| blob \| history
sim/m32r/sim-if.c		diff \| blob \| history
sim/m68hc11/interp.c		diff \| blob \| history
sim/mcore/interp.c		diff \| blob \| history
sim/microblaze/interp.c		diff \| blob \| history
sim/mips/interp.c		diff \| blob \| history
sim/mn10300/interp.c		diff \| blob \| history
sim/moxie/interp.c		diff \| blob \| history
sim/msp430/msp430-sim.c		diff \| blob \| history
sim/or1k/sim-if.c		diff \| blob \| history
sim/pru/interp.c		diff \| blob \| history
sim/riscv/interp.c		diff \| blob \| history
sim/sh/interp.c		diff \| blob \| history
sim/v850/interp.c		diff \| blob \| history

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