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(parent: 0989465) | patch
back.verilog: do not rename internal signals.
authorwhitequark <cz@m-labs.hk>
Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)
committerwhitequark <cz@m-labs.hk>
Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)
commit88afdcfc70b0e33ed9943155e20e96719aabccf6
treec1029d491da24921e10ba4fff6b0688eea35473btree
parent0989465cdfc8fa1ad059d436f913ed64c9d9a814commit | diff
back.verilog: do not rename internal signals.

_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
nmigen/back/verilog.py diff | blob | history