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(parent: 5c85236) | patch
power: Added support for CR, XER, FPSR, MSR, PTCR Registers
authorPhanikiran Harithas <phanikiran.harithas@gmail.com>
Sun, 10 Jun 2018 08:19:58 +0000 (13:49 +0530)
committerGautham R. Shenoy <ego@linux.vnet.ibm.com>
Tue, 12 Jun 2018 04:51:37 +0000 (10:21 +0530)
commit88b78aceeb23e4a1494915b2143467eff5017ed8
tree21d9cd4f2368e78ef0412efab5b226e97fcc608btree
parent5c85236cd217b0becdb083316a5cce9ce63578fecommit | diff
power: Added support for CR, XER, FPSR, MSR, PTCR Registers

Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.

In particular, annotate the bits of MSR and PTCR for future use.

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608
src/arch/power/miscregs.hh diff | blob | history
src/arch/power/system.cc diff | blob | history