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(parent: d21a07c) | patch
verilog: handle empty generate statement by removing gen_stmt_or_null...
authorEddie Hung <eddie@fpgeh.com>
Mon, 11 May 2020 17:20:33 +0000 (10:20 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 25 May 2020 14:36:53 +0000 (07:36 -0700)
commit88bddb37c91e8fe136e5c9cc2ade20fadccd1946
treed6a822ef14477b462f84ff675e7ffc890936839atree
parentd21a07c7b5ef57de5428e5f7913338af582146b5commit | diff
verilog: handle empty generate statement by removing gen_stmt_or_null...

... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
frontends/verilog/verilog_parser.y diff | blob | history