git.libre-soc.org Git - yosys.git/commit

SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.

frontends/verilog/verilog_parser.y		diff \| blob \| history
tests/simple/run-test.sh		diff \| blob \| history
tests/tools/autotest.sh		diff \| blob \| history
tests/various/implicit_ports.sv	[new file with mode: 0644]	blob
tests/various/implicit_ports.ys	[new file with mode: 0644]	blob