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litedram: Add orangecrab-85-0.2 target
authorMatt Johnston <matt@codeconstruct.com.au>
Fri, 13 Aug 2021 02:07:15 +0000 (10:07 +0800)
committerMatt Johnston <matt@codeconstruct.com.au>
Fri, 14 Jan 2022 01:36:03 +0000 (09:36 +0800)
commit8901e84d8dcc1cee2bc1af7382b05e74f22d65c7
tree42278b662f8b4f17dbe0d5e30be9430d3cb9d52btree
parent08021ae28e4608b14399f56649463a7a3ebd2595commit | diff
litedram: Add orangecrab-85-0.2 target

Parameters are based on
https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py
and litex-boards orangecrab.py

rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here.

Generated with litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
litedram/gen-src/generate.py diff | blob | history
litedram/gen-src/orangecrab-85-0.2.yml [new file with mode: 0644] blob
litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl [new file with mode: 0644] blob
litedram/generated/orangecrab-85-0.2/litedram_core.init [new file with mode: 0644] blob
litedram/generated/orangecrab-85-0.2/litedram_core.v [new file with mode: 0644] blob