anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW
authorJason Ekstrand <jason.ekstrand@intel.com>
Mon, 12 Sep 2016 19:58:38 +0000 (12:58 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Thu, 15 Sep 2016 00:53:16 +0000 (17:53 -0700)
commit89a96c8f43370cc84adf92ab32e3de302a1fa1d0
treeb5262dfcae89b3be50ceb341d0f8d8aba70c42ec
parenta814e18c96ccc70473103cf08a675265f0d1b3c9
anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW

Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.

Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
src/intel/genxml/gen75.xml
src/intel/vulkan/genX_cmd_buffer.c