projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: af23195) | patch
add rvc_sp redirection/offset overload
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 15 Oct 2018 06:49:26 +0000 (07:49 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 15 Oct 2018 06:49:26 +0000 (07:49 +0100)
commit8a40c15a5fb9a49757e482ce7e604c4ff9990975
tree1cb7ba7d3e3c1f006d9150c4191601be1334f76ftree
parentaf23195ea1c3ed1acb55ed520597ce54fb1c77aecommit | diff
add rvc_sp redirection/offset overload

also found weird bug where RVC_FRS1/2 were not being detected,
how it was not found earlier is a mystery, code should not
have compiled!
id_regs.py diff | blob | history
riscv/insn_template_sv.cc diff | blob | history
riscv/sv_decode.h diff | blob | history
Simple-V augmented version of spike