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arch-arm: Using explicit invalidation in TLB
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 11 Dec 2017 13:20:07 +0000 (13:20 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 18 Apr 2018 14:42:10 +0000 (14:42 +0000)
commit8a690593f4f4980df3fc5f4609674b1e3e62b1bc
tree37d27c1432511369c758ae034c240f313e76ba6btree
parent5cebd91336cbfbf46d6bffe9a01b7eea55e62f44commit | diff
arch-arm: Using explicit invalidation in TLB

When setting TLB related MiscRegs, using explicit TLB regs invalidation
rather than implicit switch-case fallthrough

Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10041
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/arch/arm/isa.cc diff | blob | history