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(parent: cb5b4ac) | patch
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multipl...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Aug 2018 06:32:32 +0000 (08:32 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Aug 2018 06:32:32 +0000 (08:32 +0200)
commit8a69a47e7b502eea6f95c11e316836aec125ea82
tree6fe385b3ffd043101f2371feecf02bc6d1c0c221tree
parentcb5b4ac468ff5ddd1d1206d0bb9e721bde98ae94commit | diff
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
litex/soc/cores/cpu/lm32/core.py diff | blob | history
litex/soc/cores/cpu/lm32/verilog/config/lm32_config.v [new file with mode: 0644] blob
litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v [new file with mode: 0644] blob
litex/soc/cores/cpu/lm32/verilog/lm32_config.v [deleted file] blob | history