arm: properly handle RES0/1 for SCTLRs
authorCurtis Dunham <Curtis.Dunham@arm.com>
Mon, 7 May 2018 23:06:08 +0000 (18:06 -0500)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Thu, 3 Jan 2019 10:38:22 +0000 (10:38 +0000)
commit8a9e0079e7fc89c7abbf7d360cd1707d11cd3df0
treec327a2d7211e1c3ddf26e531c55d65ad7c6d4d1d
parentff7fc9de6955ba3e00898eb703b3da1a15fb417c
arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/arch/arm/isa.cc
src/arch/arm/miscregs.cc