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(parent: 114d468) | patch
nvc0/ir: fill offset in properly for TXD
authorIlia Mirkin <imirkin@alum.mit.edu>
Sat, 5 Jul 2014 05:24:38 +0000 (01:24 -0400)
committerIlia Mirkin <imirkin@alum.mit.edu>
Tue, 8 Jul 2014 04:14:33 +0000 (00:14 -0400)
commit8aa34dc9cb1f4b1b17e49da98e54066832afc98e
tree8f83f094f3900afb83b5c1da080ad84ede7e70a0tree
parent114d46829d10c826927cabc1ca14884a4ee249f7commit | diff
nvc0/ir: fill offset in properly for TXD

Apparently TXD wants its offset differently than TEX, accepting it in
the upper bits of the layer index. Unclear what happens when this is
combined with indirect sampler indexing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp diff | blob | history