mem: Add a master ID to each request object.
authorAli Saidi <Ali.Saidi@ARM.com>
Sun, 12 Feb 2012 22:07:38 +0000 (16:07 -0600)
committerAli Saidi <Ali.Saidi@ARM.com>
Sun, 12 Feb 2012 22:07:38 +0000 (16:07 -0600)
commit8aaa39e93dfe000ad423b585e78a4c2ee7418363
tree0f7b6d1efb630745bd6bf6af05a722a08c8640cb
parent7e104a1af235823e3d641a972ea920937f7ec67d
mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
50 files changed:
src/arch/arm/isa.cc
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/arch/x86/intmessage.hh
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/cpu/base.cc
src/cpu/base.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.cc
src/cpu/checker/cpu.hh
src/cpu/checker/cpu_impl.hh
src/cpu/inorder/resources/cache_unit.cc
src/cpu/inorder/resources/fetch_unit.cc
src/cpu/inorder/resources/tlb_unit.hh
src/cpu/o3/fetch_impl.hh
src/cpu/simple/atomic.cc
src/cpu/simple/base.cc
src/cpu/simple/timing.cc
src/cpu/testers/directedtest/DirectedGenerator.cc
src/cpu/testers/directedtest/DirectedGenerator.hh
src/cpu/testers/directedtest/InvalidateGenerator.cc
src/cpu/testers/directedtest/RubyDirectedTester.py
src/cpu/testers/directedtest/SeriesRequestGenerator.cc
src/cpu/testers/memtest/MemTest.py
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/memtest/memtest.hh
src/cpu/testers/networktest/NetworkTest.py
src/cpu/testers/networktest/networktest.cc
src/cpu/testers/networktest/networktest.hh
src/cpu/testers/rubytest/Check.cc
src/cpu/testers/rubytest/RubyTester.cc
src/cpu/testers/rubytest/RubyTester.hh
src/cpu/testers/rubytest/RubyTester.py
src/dev/io_device.cc
src/dev/io_device.hh
src/mem/cache/cache_impl.hh
src/mem/cache/prefetch/Prefetcher.py
src/mem/cache/prefetch/base.cc
src/mem/cache/prefetch/base.hh
src/mem/cache/prefetch/ghb.cc
src/mem/cache/prefetch/ghb.hh
src/mem/cache/prefetch/stride.cc
src/mem/cache/tags/iic.cc
src/mem/port.cc
src/mem/request.hh
src/mem/ruby/recorder/CacheRecorder.cc
src/mem/ruby/system/RubyPort.cc
src/sim/system.cc
src/sim/system.hh