targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 11 Feb 2020 16:44:24 +0000 (17:44 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 11 Feb 2020 16:44:24 +0000 (17:44 +0100)
commit8b5cc345538ae1138dab8c405c9c91c2f986113c
tree82f28f34495d3ee23f1edf5841049f972dcaa841
parent240a55bace286fadafd39c56681e7be672367f76
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
litex/boards/targets/arty.py
litex/boards/targets/genesys2.py
litex/boards/targets/kc705.py
litex/boards/targets/netv2.py
litex/boards/targets/nexys4ddr.py
litex/boards/targets/nexys_video.py
litex/boards/targets/simple.py
litex/boards/targets/versa_ecp5.py