cores/icap/ICAPBitstream: add source ready signal.
authorJan Kowalewski <jkowalewski@antmicro.com>
Fri, 18 Oct 2019 07:33:31 +0000 (09:33 +0200)
committerJan Kowalewski <jkowalewski@antmicro.com>
Fri, 18 Oct 2019 07:33:31 +0000 (09:33 +0200)
commit8b5da9c62310cbc8fc84591ed50d1eaaf1df7a6a
tree6650b0efca0ad3549ba3064597f9a6ed70e114fd
parent626533ce9d84ba081aa320dd330f5f0d800333b0
cores/icap/ICAPBitstream: add source ready signal.
litex/soc/cores/icap.py