Detect illegal port declaration, e.g input/output/inout keyword must be the first.
authorUdi Finkelstein <github@udifink.com>
Wed, 6 Jun 2018 19:27:25 +0000 (22:27 +0300)
committerUdi Finkelstein <github@udifink.com>
Wed, 6 Jun 2018 19:27:25 +0000 (22:27 +0300)
commit8b7580b0a152ec937abb1510abf5f2d7cd3b7acb
treef9a62e951c77a20749fdbf3d1df76786b7a298c7
parent270c1814b5bcab0f0b54f05b4856380b57617a69
Detect illegal port declaration, e.g input/output/inout keyword must be the first.
frontends/verilog/verilog_parser.y